Overview
We’re hosting a hands-on tutorial on the ZigZag project at ISPASS 2023 in Raleigh, North Carolina.
This tutorial will take place on Sunday April 23rd from 8 AM - 12 PM.
What is the ZigZag project?
Building efficient embedded deep learning (DL) systems requires a tight co-design between DNN algorithms, hardware, and algorithm-to-hardware scheduling, a.k.a. dataflow or mapping. Different hardware architectures (single-core or multi-core accelerators) are being designed, supporting many different scheduling possibilities, for different optimizing targets (energy,latency, memory footprint). However, owing to the large joint design space, finding an optimal solution through RTL simulation or physical implementation becomes infeasible. To tackle this problem, a unified high-level DL accelerator design space exploration (DSE) framework infrastructure, called ZigZag, is proposed.
ZigZag targets rapid DSE for DNN accelerator platforms supporting an broad set of hardware architectures and workload scheduling scenarios beyond other existing frameworks.
Stream is an extension of ZigZag capable of modeling multi-core DNN acceleration employing fine-grained layer-fused processing.
What will you learn in this tutorial?
This tutorial will introduce the unified DSE framework infrastructure and demonstrate the capabilities of ZigZag and Stream by guiding participants through several DSE experiments step-by-step. By the end of the tutorial, participants will have a complete view of the DL accelerator and scheduling design space and will have gained enough knowledge to deploy the open-source frameworks as their own personal customized DSE tool.
Contents
| Time | Content |
|---|---|
| 8.30 AM - 8.50 AM | Introduction of the ZigZag project |
| 8.50 AM - 9.30 AM | Lab 1: Assessing the hardware performance of running a DNN on a single-core accelerator with fixed mappings |
| 9.30 AM - 10.00 AM | Lab 2: Optimizing mapping performance of a single-core accelerator with built-in automatic mapping exploration |
| 10.00 AM - 10.30 AM | Break |
| 10.30 AM - 11.00 AM | Lab 3: Understanding & customizing the hardware architecture definition for other dataflows |
| 11.00 AM - 11.45 AM | Lab 4: Expanding the hardware to multi-core architectures with layer-fused processing using Stream |
| 11.45 AM - 12.00 PM | Concluding remarks |
Slides
Organizers
| People |
|---|
| Arne Symons |
| Linyan Mei |
| Dr. Guilherme Paim |
| Prof. Marian Verhelst |
